Thermal management has become the critical bottleneck for device performance. As the industry shifts to on-device Edge AI, the integration of Neural Processing Units (NPUs) drives Total Design Power (TDP) well beyond what passive architectures were built to handle, generating heat fluxes that vapor chambers and graphite sheets can no longer dissipate. Traditional passive cooling relies entirely on surface area, phase-change cycles, and capillary wicking, and all three hit a hard physical wall in ultra-thin form factors. Once capillary limits are reached, the wick dries out, thermal resistance spikes, and the SoC throttles.
Sustaining Edge AI performance in sleek form factors means rethinking the thermal stack from the ground up. Manufacturers need to move from passive heat sinks to active, miniaturized microfluidic cooling. In the next generation of smart devices, active micro-cooling will separate products that hold peak performance from those that plateau at their thermal limits.
Our microfluidic cooling solution replaces the passive spread of heat with an active, closed-loop system that mechanically routes thermal energy away from the source. It brings the microchannel liquid cooling architecture used in AI server racks down to the scale of smartphones, laptops, and AR/VR wearables.
Three components work as one: a piezoelectric micropump drives high-precision forced convection, a custom microchannel cold plate extracts heat at the silicon level, and the BOS1931 piezo driver powers the loop on a milliwatt budget. Heat is captured at the source, routed deterministically, and rejected where it belongs, all in profiles where passive vapor chambers saturate and fail.
Higher Heat Transfer Coefficient
Traditional ultra-thin vapor chambers struggle to keep up as they reach their capillary limit under load. This reduces the solution’s heat transfer coefficient that forces your SoC to throttle.
By using forced convection through precision microchannels, our piezo micropump liquid cooling solution maximizes heat extraction at the source.
This allows your device to sustain the massive power bursts generated by AI tasks, bringing data-center-level thermal management to the most constrained form factors.
Complete Control Over Heat Movement
Passive isothermal spreading in ultra-thin vapor chambers often leads to thermal contamination of sensitive batteries and displays while diluting the temperature gradient (ΔT) necessary for effective dissipation.
Our active liquid solution replaces this reactive spreading with an architecture where you decide where to move the heat, mechanically directing it away from critical components toward optimized chassis exit points. By maximizing the localized ΔT at these specific boundaries, we accelerate heat rejection to ambient and unlock the sustained TDP headroom required for intensive AI workloads in sub-0.5mm form factors.
Gravity-Agnostic Cooling
Passive ultra-thin vapor chambers rely on compressed wick structures that are highly susceptible to capillary saturation. When forced to fight gravitational head in tilted or vertical orientations, these passive systems frequently suffer from thermal dry-out, resulting in immediate performance throttling.
Our piezo-driven active cooling eliminates this instability by using mechanical pressure to force liquid transport across the entire device. This ensures gravity-agnostic cooling, unlocking the sustained performance potential of next-gen SoCs in the most constrained mobile and wearable form factors.
Recommended Part
For microfluidic cooling applications, we recommend the Boréas Technologies BOS1931. This single-chip driver delivers the high-voltage, ultra-low-power performance needed to run piezoelectric micropumps without adding heat to an already strained thermal budget.
Built on our CapDrive™ architecture, the BOS1931 recovers energy from the piezo actuator on each cycle, delivering up to 10x lower power consumption than competing solutions. With a sub-300 µs start-up time and a 2.1 x 1.7 x 0.625 mm footprint, it reacts instantly to thermal spikes while saving critical PCB space in the most constrained build volumes.
